1. Field of the Invention
The present invention relates to an improved method for manufacturing a semiconductor memory cell and, more particularly, this invention relates to an improved method for manufacturing a bit line via hole in a semiconductor memory cell.
2. DESCRIPTION OF THE RELATED ART
The present invention is directed to a method for manufacturing a bit line via hole for a memory cell in a semiconductor substrate having a capacitor located above an MOS transistor and a bit line above the capacitor wherein a lower capacitor plate is connected to a first source/drain (S/D) region of the transistor. In order to achieve high packing density in such DRAM memory cells, it is desirable to design the cell so that the bit line is located above a stacked capacitor. In these designs the lower capacitor plate is connected to a first S/D region of the transistor.
The problem with prior art designs of this type is in the difficulty encountered in producing the bit line contact at the S/D region of the transistor through the capacitor level. The capacitors cannot fill the entire cell area but must leave room for the bit line contact which must connect at least one but usually two memory cells. The spacing of the capacitors from the edge of the bit line via hole thus defines the effective space requirements for the bit line contact--in addition to the size of the via hole itself--and should thus be as small as possible. Adequate insulation must also be provided between the bit line and the lower capacitor plate and the cell plate. It is also desirable to have the bit line contact overlap the gate insulation and the field insulation to prevent these insulations from being damaged during the manufacturing process.
Various methods for manufacturing memory cells are known in the art. An article by Itoh, et al. in VLSI Symposium 1991, at page 9, describes a manufacturing process for a bit line via hole wherein a spacer is produced at the side walls of the via hole for insulation and structuring of the cell plate before deposition of the insulation layer is foregone. In this design, however, the actual contact area is greatly diminished since the spacer must have at least the thickness of the necessary insulating distance. Furthermore, self-alignment relative to the gate and/or field oxide is not provided in this design.
An article by Kuesters, et al. in Journal de Physique, C4, vol. 49, September 1988, page C4-503 and the corresponding European patent application No. 0 258 657 from the same individuals disclose thermally oxidizing the exposed edge of the cell plate instead of forming spacers thus providing a relatively large contact area. Japanese application No. JP 2-79 462 illustrates a DRAM memory cell where a bit line is connected via a pad electrode to the S/D region that may be partially overlapped by the capacitor plates. The cell plate is thereby structured with a photo technique. Alignment errors, therefore, must be taken into account with this design.
All of these known methods require a photo technique for producing the bit line via hole, i.e., a photoresist layer must be applied, exposed and developed, which, therefore, requires consideration of alignment tolerances.
An object of the present invention is to provide a method for manufacturing a bit line via hole for a memory cell without utilizing a photo technique while maintaining an adequate insulation distance from the capacitor.